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INTEGRATED CIRCUITS
74F219A 64-bit TTL bipolar RAM, non-inverting (3-State)
Product specification IC15 Data Handbook 1996 Jan 05
Philips Semiconductors
Philips Semiconductors
Product specification
64-bit TTL bipolar RAM, non-inverting (3-State)
74F219A
FEATURES
* High speed performance * Replaces 74F219 * Address access time: 8ns max vs 28ns for 74F219 * Power dissipation: 4.3mW/bit typ * Schottky clamp TTL * One chip enable * Non-Inverting outputs (for inverting outputs see 74F189A) * 3-state outputs * 74F219A in 150 mil wide SO is preferred options for new designs * C3F219A in 300 mil wide SOL replaces 74F219 in existing
designs
APPLICATIONS
* Scratch pad memory * Buffer memory * Push down stacks * Control store
PIN CONFIGURATION
A0 1 CE 2 WE 3 D0 4 Q0 5 D1 6 16 VCC 15 A1 14 A2 13 A3 12 D3 11 Q3 10 D2 9 Q2
DESCRIPTION
The 74F219A is a high speed, 64-bit RAM organized as a 16-word by 4-bit array. Address inputs are buffered to minimize loading and are fully decoded on chip. The outputs are in high impedance state whenever the chip enable (CE) is high. The outputs are active only in the READ mode (WE = high) and the output data is the complement of the stored data.
Q1 7 GND 8
SF00307
TYPE 74F219A
TYPICAL ACCESS TIME 5.0ns
TYPICAL SUPPLY CURRENT(TOTAL) 55mA
ORDERING INFORMATION
ORDER CODE DESCRIPTION 16-pin plastic Dual In-line Package 16-pin plastic Small Outline (150mil) 16-pin plastic Small Outline Large (300mil) COMMERCIAL RANGE VCC = 5V 10%, Tamb = 0C to +70C N74F219AN N74F219AD C3F219AD DRAWING NUMBER SOT38-4 SOT109-1 SOT162-1
INPUT AND OUTPUT LOADING AND FAN OUT TABLE
PINS D0 - D3 A0 - A3 CE WE Q0 - Q3 Data inputs Address inputs Chip enable input (active low) Write enable input (active low) Data outputs DESCRIPTION 74F (U.L.) HIGH/LOW 1.0/1.0 1.0/1.0 1.0/2.0 1.0/2.0 150/40 LOAD VALUE HIGH/LOW 20A/0.6mA 20A/0.6mA 20A/1.2mA 20A/1.2mA 3mA/24mA
NOTE: One (1.0) FAST unit load is defined as: 20A in the high state and 0.6mA in the low state.
1996 Jan 05
2
853-1308 16196
Philips Semiconductors
Product specification
64-bit TTL bipolar RAM, non-inverting (3-State)
74F219A
LOGIC SYMBOL
4 6 10 12
IEC/IEEE SYMBOL
1 15 14 13 2 3 1 G1 1 EN [READ] 1 C2 [WRITE] A,2D A 5 7 9 11 RAM 16X4 0 A 0 15
D0 D1 D2 D3 1 15 14 13 2 3 A0 A1 A2 A3 CE WE Q0 Q1 Q2 Q3
4 6 10
VCC = pin 16 GND = pin 8
5
7
9
11 12
SF00308
SF00301
LOGIC DIAGRAM
D0 D1 D2 D3 4 6 10 12 3 Data buffers 2 WE CE
A0 A1 A2 A3
1 15 14 13 Decoder Drivers Address Decoder 16-word x 4-bit memory cell array
Output buffers 5 VCC = Pin 16 GND = Pin 8 7 9 11
Q0 Q1 Q2 Q3
SF00309
FUNCTION TABLE
INPUTS CE L L L H WE H L L X Dn X L H X OUTPUT Qn Stored data High impedance High impedance High impedance OPERATING MODE Read Write "0" Write "1" Disable input
NOTES: H = High voltage level L = Low voltage level X = Don't care
1996 Jan 05
3
Philips Semiconductors
Product specification
64-bit TTL bipolar RAM, non-inverting (3-State)
74F219A
ABSOLUTE MAXIMUM RATINGS
(Operation beyond the limit set forth in this table may impair the useful life of the device. Unless otherwise noted these limits are over the operating free-air temperature range.) SYMBOL VCC VIN IIN VOUT IOUT Tamb Tstg Supply voltage Input voltage Input current Voltage applied to output in high output state Current applied to output in low output state Operating free-air temperature range Storage temperature range PARAMETER RATING -0.5 to +7.0 -0.5 to +7.0 -30 to +5 -0.5 to VCC 48 0 to +70 -65 to +150 UNIT V V mA V mA C C
RECOMMENDED OPERATING CONDITIONS
SYMBOL VCC VIH VIL IIk IOH IOL Tamb Supply voltage High-level input voltage Low-level input voltage Input clamp current High-level output current Low-level output current Operating free-air temperature range 0 PARAMETER LIMITS MIN 4.5 2.0 0.8 -18 -3 24 +70 NOM 5.0 MAX 5.5 UNIT V V V mA mA mA C
DC ELECTRICAL CHARACTERISTICS
(Over recommended operating free-air temperature range unless otherwise noted.) SYMBOL PARAMETER TEST CONDITIONS1 MIN VOH High-level output voltage VCC = MIN, VIL = MAX VIH = MIN, IOH = MAX VOL Low-level output voltage VCC = MIN, VIL = MAX VIH = MIN, IOL = MAX VIK II IIH IIL Input clamp voltage Input current at maximum input voltage High-level input current Low-level input current Offset output current, high-level voltage applied Offset output current, low-level voltage applied Short-circuit output current3 Supply current (total) Input capacitance others CE, WE IOZH IOZL IOS ICC CIN VCC = MAX, VI = 2.7V VCC = MAX, VI = 0.5V VCC = MAX VCC = MAX, CE = WE = GND VCC = 5V, VIN = 2.0V -60 55 4 VCC = MIN, II = IIK VCC = MAX, VI = 7.0V VCC = MAX, VI = 2.7V VCC = MAX, VI = 0.5V LIMITS TYP2 MAX V 3.4 0.35 0.35 -0.73 0.50 0.50 -1.2 100 20 -0.6 -1.2 50 -50 -150 80 V V V V A A mA mA A A mA mA pF UNIT
10%VCC 5%VCC 10%VCC 5%VCC
2.4 2.7
COUT Output capacitance VCC = 5V, VOUT = 2.0V 7 pF NOTES: 1. For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions for the applicable type. 2. All typical values are at VCC = 5V, Tamb = 25C. 3. Not more than one output should be shorted at a time. For testing IOS, the use of high-speed test apparatus and/or sample-and-hold techniques are preferable in order to minimize internal heating and more accurately reflect operational values. Otherwise, prolonged shorting of a high output may raise the chip temperature well above normal and thereby cause invalid readings in other parameter tests. In any sequence of parameter tests, IOS tests should be performed last. 1996 Jan 05 4
Philips Semiconductors
Product specification
64-bit TTL bipolar RAM, non-inverting (3-State)
74F219A
AC ELECTRICAL CHARACTERISTICS
LIMITS SYMBOL PARAMETER TEST CONDITION Tamb = +25C VCC = +5.0V CL = 50pF, RL = 500 MIN tPLH tPHL tPZH tPZL tPHZ tPLZ tPZH tPZL tPHZ tPLZ Disable time CE to Qn Write recovery time Disable time WE to Qn Enable time WE to Qn Access time Propagation delay An to Qn Enable time CE to Qn Waveform 1 Waveform 2 Waveform 3 Waveform 4 Waveform 4 2.5 2.0 1.5 2.5 2.5 1.5 2.0 3.0 3.0 1.5 TYP 5.0 4.5 3.0 4.0 4.5 3.0 3.5 4.5 5.0 3.5 MAX 8.0 8.0 6.0 7.0 7.0 5.5 6.5 7.5 8.0 6.0 Tamb = 0C to +70C VCC = +5.0V 10% CL = 50pF, RL = 500 MIN 2.5 2.0 1.5 2.0 2.0 1.0 1.5 2.5 2.5 1.5 MAX 8.0 8.0 7.0 7.5 8.0 6.0 7.0 8.0 9.0 7.0 ns ns ns ns ns UNIT
AC SETUP REQUIREMENT
LIMITS SYMBOL PARAMETER TEST CONDITION Tamb = +25C VCC = +5.0V CL = 50pF, RL = 500 MIN tsu(H) tsu(L) th(H) th(L) tsu(H) tsu(L) th(H) th(L) tsu(L) th(L) tw(L) Setup time, high or low An to WE Hold time, high or low An to WE Setup time, high or low Dn to WE Hold time, high or low Dn to WE Setup time, low CE (falling edge) to WE (falling edge) Hold time, low WE (falling edge) to WE (rising edge) Pulse width, low WE Waveform 4 Waveform 4 Waveform 4 Waveform 4 Waveform 4 Waveform 4 Waveform 4 4.5 4.5 0 0 8.0 7.5 0 0 0 6.5 7.0 TYP MAX Tamb = 0C to +70C VCC = +5.0V 10% CL = 50pF, RL = 500 MIN 5.0 5.0 0 0 9.0 8.5 0 0 0 7.5 8.0 MAX ns ns ns ns ns ns ns UNIT
1996 Jan 05
5
Philips Semiconductors
Product specification
64-bit TTL bipolar RAM, non-inverting (3-State)
74F219A
AC WAVEFORMS FOR READ CYCLES
For all waveforms, VM = 1.5V.
An
VM tPHL
Qn
VM tPLH
SP000310
Waveform 1. Read cycle, address access time
CE
VM tPZH
Qn tPZL
VM
SP000311
Waveform 2. Read cycle, chip enable access time
CE
VM tPHZ
Qn
VM tPLZ
SP000312
Waveform 3. Read cycle, chip disable time
1996 Jan 05
6
Philips Semiconductors
Product specification
64-bit TTL bipolar RAM, non-inverting (3-State)
74F219A
AC WAVEFORMS FOR WRITE CYCLE
An VM tsu (H or L) th (H or L) VM
Dn
VM
VM
VM
tsu ( L)
th (H or L) VM
CE
VM tsu (H or L) tw ( L) th ( L)
WE
VM
VM
tPHZ
tPZH
Qn
Hi-Z
VM tPLZ tPZL VM
NOTE: For all waveforms, VM = 1.5V. Waveform 4. Write cycle
SP000313
TEST CIRCUIT AND WAVEFORM
VCC NEGATIVE PULSE VIN PULSE GENERATOR RT D.U.T. VOUT 90% VM 10% tTHL (tf ) CL RL tw VM 10% tTLH (tr ) 0V 90% AMP (V)
tTLH (tr ) 90% POSITIVE PULSE VM 10% tw
tTHL (tf ) AMP (V) 90% VM 10% 0V
Test Circuit for Totem-Pole Outputs DEFINITIONS: RL = Load resistor; see AC ELECTRICAL CHARACTERISTICS for value. CL = Load capacitance includes jig and probe capacitance; see AC ELECTRICAL CHARACTERISTICS for value. RT = Termination resistance should be equal to ZOUT of pulse generators.
Input Pulse Definition INPUT PULSE REQUIREMENTS family amplitude VM 74F 3.0V 1.5V rep. rate 1MHz tw 500ns tTLH 2.5ns tTHL 2.5ns
SF00006
1996 Jan 05
7
Philips Semiconductors
Product specification
64-Bit TTL bipolar RAM, non-inverting (3-State)
74F219A
DIP16: plastic dual in-line package; 16 leads (300 mil); long body
SOT38-1
1996 Jan 05
8
Philips Semiconductors
Product specification
64-Bit TTL bipolar RAM, non-inverting (3-State)
74F219A
SO16: plastic small outline package; 16 leads; body width 3.9 mm
SOT109-1
1996 Jan 05
9
Philips Semiconductors
Product specification
64-Bit TTL bipolar RAM, non-inverting (3-State)
74F219A
SO16: plastic small outline package; 16 leads; body width 7.5 mm
SOT162-1
1996 Jan 05
10
Philips Semiconductors
Product specification
64-Bit TTL bipolar RAM, non-inverting (3-State)
74F219A
NOTES
1996 Jan 05
11
Philips Semiconductors
Product specification
64-bit TTL bipolar RAM, non-inverting (3-State)
74F219A
DEFINITIONS
Data Sheet Identification
Objective Specification
Product Status
Formative or in Design
Definition
This data sheet contains the design target or goal specifications for product development. Specifications may change in any manner without notice. This data sheet contains preliminary data, and supplementary data will be published at a later date. Philips Semiconductors reserves the right to make changes at any time without notice in order to improve design and supply the best possible product. This data sheet contains Final Specifications. Philips Semiconductors reserves the right to make changes at any time without notice, in order to improve design and supply the best possible product.
Preliminary Specification
Preproduction Product
Product Specification
Full Production
Philips Semiconductors and Philips Electronics North America Corporation reserve the right to make changes, without notice, in the products, including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. LIFE SUPPORT APPLICATIONS Philips Semiconductors and Philips Electronics North America Corporation Products are not designed for use in life support appliances, devices, or systems where malfunction of a Philips Semiconductors and Philips Electronics North America Corporation Product can reasonably be expected to result in a personal injury. Philips Semiconductors and Philips Electronics North America Corporation customers using or selling Philips Semiconductors and Philips Electronics North America Corporation Products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors and Philips Electronics North America Corporation for any damages resulting from such improper use or sale. Philips Semiconductors 811 East Arques Avenue P.O. Box 3409 Sunnyvale, California 94088-3409 Telephone 800-234-7381 Philips Semiconductors and Philips Electronics North America Corporation register eligible circuits under the Semiconductor Chip Protection Act. (c) Copyright Philips Electronics North America Corporation 1996 All rights reserved. Printed in U.S.A. (print code) Document order number: Date of release: July 1994 9397-750-05098

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